\subsubsection{Circuit Design Techniques} 
\label{sec:circuit_design} 
Standard circuit design techniques that have been widely adopted for
standard CMOS are expected to be sub-optimal for TFETs.  This is
because the device characteristics of TFETs are significantly
different compared to standard transistors. In this research, we 
propose to carry out a comprehensive exploration of standard cell 
design techniques considering unique properties of TFETs. 

\begin{enumerate}[i] \itemsep1pt \parskip0pt \parsep0pt

\item Combinational Logic Design: To optimize the performance and energy
efficiency of the circuits, the strength of p- and n- transistors
needs to be balanced. The standard technique achieves this balance by
optimizing the transistor widths.  However, p-type TFETs have
been shown to have much lower performance compared to their n-type
counterparts~\cite{Khatami-TED2009-TFETCircuits}. As a result,
this technique can lead to a large increase in the layout area. We
will explore alternative techniques like (a) cell design using p-TFETs
with lower threshold voltage and (b) exploring topologies which avoid
the use of large number of stacked p-TFETs. Both these techniques are
expected to reduce the cell area and lower interconnect capacitance. 
The new cell options will provide flexibility during the
synthesis operation and lead to an optimal design solution.

\item Sequential Logic Design: An important class of circuits, which
are expected to be critically affected by the unique properties of
TFETs are flip-flops. The most common topology used in the
state-of-the-art designs is based on transmission
gates~\cite{RabaeyBook}. However, this topology may not be optimal for TFETs due
to their asymmetric output characteristics. Alternate topologies such
as those based on tri-state inverter~\cite{RabaeyBook} will be analyzed. New
techniques to implement the asynchronous reset will also be
explored. Typically, the retention of the logic state in a flip-flop
limits the scaling of the stand-by $V_DD$. In order to minimize the
stand-by leakage power, exploration of flip-flop topologies with lower
retention voltage will be carried out. 

\item Layout Optimization: TFETs have been shown to achieve higher
performance with two different but compatible materials used for the
source and channel~\cite{Datta-MicroRel2014-TFET}.  As a result, TFETs need to be fabricated by
growing the channel on the source and the drain on the channel.  The
vertical structure of TFETs requires circuit layout design that is
drastically different compared to the standard transistors (which have
a lateral device structure).  In this research, we propose to explore
new layout techniques for a broad spectrum of cells based on vertical transistors 
with an objective to minimize the area and the interconnect capacitance.  
Interconnect/contact resistance and capacitance will be obtained from the layouts, which will be 
used to quantify the performance of various cells.
\end{enumerate}